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An efficient fully differential voltage comparator
Ashima Gupta1, Alpana Agarwal2.
With the compactness of the devices, the circuits are required with less delay,
less area and less power consumption. An efficient fully digital-in-notion
differential voltage comparator with the opamp-less approach is implemented in
this paper. This comparator detects a small input voltage difference, i.e.,
resolution of this comparator is 8-bits and amplifies the output to either of the
two different logic levels high or low, i.e., 1 or 0 respectively. Though dynamic
latched comparators are quite attractive, they suffer from high power
consumption and large offset voltages. In addition to the low power consumption,
this comparator is extremely cost-effective as an analogue circuit has been
designed digitally and fabricated in a digital process. The comparator is designed
and implemented in the Cadence Virtuoso tool using SCL 180 nm
Complementary Metal Oxide Semiconductor (CMOS) digital process at a supply
of 1.8 V and a load capacitance of 1 pF.
Affiliation:
- Thapar Institute of Engineering and Technology, India
- Thapar Institute of Engineering and Technology, India
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Indexation |
Indexed by |
MyJurnal (2019) |
H-Index
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0 |
Immediacy Index
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0.000 |
Rank |
0 |
Indexed by |
Scopus (SCImago Journal Rankings 2016) |
Impact Factor
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- |
Rank |
Q3 (Engineering (miscellaneous)) |
Additional Information |
0.193 (SJR) |
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