The last few years have witnessed great deal of research activities in the area of reversible logic; the intrinsic functionality to reduce the power dissipation that has been the main requirement in the low power digital circuit design has garnered more attraction to this field. In this paper various power gating techniques for power minimization in adder and 4 bit serial in serial out (SISO) shift register circuits is proposed. The work also analyze various leakage reduction approaches such as sleep approach, sleepy stack approach, dual sleep technique and zig-zag technique for gate diffusion input technique, self resetting gate diffusion input technique for complementary metal oxide semi conductor (CMOS) technology and forced stack and multiplexer based SISO registers. A 4 bit SISO and full adder was designed in a cadence virtuoso 180 nm technology and the simulated results show the trade-off between power, delay and power for the sequential circuits and the results demonstrate that minimum power consumption can be achieved when the adder and SISO are designed for clock gating.